Summary
Senior FPGA engineer with 12 years of experience leading digital design projects. Expert in VHDL, Verilog, timing closure, and process improvement. Proven leader in mentoring teams and delivering innovative embedded solutions.
Experience
- Led a team of 8 engineers to deliver a complex FPGA design project 6 weeks ahead of schedule
- Defined and improved design processes, reducing rework by 35%
- Implemented and simulated IP blocks in RTL using VHDL and SystemVerilog, increasing performance by 18%
- Analyzed test results and resolved 20+ critical issues before production release
- Authored system development plans that improved traceability and compliance
- Achieved timing closure on high-speed designs up to 600 MHz
- Mentored junior engineers and improved team productivity by 25%
- Assisted in business development through technical presentations and proposal writing
Education
Projects
Courses
- Top Secret Security Clearance, Department of Defense